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| ht46r65/ht46c65 a/d with lcd type 8-bit mcu rev. 1.80 1 july 14, 2005 features operating voltage: f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v 24 bidirectional i/o lines two external interrupt input two 16-bit programmable timer/event counter with pfd (programmable frequency divider) function lcd driver with 41 3or40 4 segments (logical output option for seg0~seg23) 8k 16 program memory 384 8 data memory ram supports pfd for sound generation real time clock (rtc) 8-bit prescaler for rtc watchdog timer buzzer output on-chip crystal, rc and 32768hz crystal oscillator halt function and wake-up feature reduce power consumption 16-level subroutine nesting 8 channels 10-bit resolution a/d converter 4-channel 8-bit pwm output shared with 4 i/o lines bit manipulation instruction 16-bit table read instruction up to 0.5 s instruction cycle with 8mhz system clock 63 powerful instructions all instructions in 1 or 2 machine cycles low voltage reset/detector function 52-pin qfp, 56-pin ssop, 100-pin qfp packages general description the ht46r65/ht46c65 are 8-bit, high performance, risc architecture microcontroller devices specifically designed for a/d product applications that interface di - rectly to analog signals and which require lcd inter - face. the mask version ht46c65 is fully pin and functionally compatible with the otp version ht46r65 device. the advantages of low power consumption, i/o flexibil - ity, timer functions, oscillator options, multi-channel a/d converter, pulse width modulation function, halt and wake-up functions, in addition to a flexible and configurable lcd interface enhance the versatility of these devices to control a wide range of applications re - quiring analog signal processing and lcd interfacing, such as electronic metering, environmental monitoring, handheld measurement tools, motor driving, etc., for both industrial and home appliance application areas. technical document tools information faqs application note ha0003e communicating between the ht48 & ht46 series mcus and the ht93lc46 eeprom ha0004e ht48 & ht46 mcu uart software implementation method ha0005e controlling the i2c bus with the ht48 & ht46 mcu series ha0047e an pwm application example using the ht46 series of mcus
block diagram ht46r65/ht46c65 rev. 1.80 2 july 14, 2005 ! ! " " # " $ % & " " ' ' ! ! ( ) ) " * $ # + $ ) ' , - ' ' , . ) + ( ! / ' / & 0 - & 0 1 2 - ' & 0 - " " ) " ) ' - ( ' , - ( - ' 3 - 2 - ' 4 - ) + + + + ' - " ' , + 4 - " 4 " ' - + 5 " - + 5 " " - / " , " 4 ( 6 7 % 1 " - ) 8 9 " $ - $ - $ 4 2 6 9 : 4 - pin assignment note: the 52-pin qfp package does not support the charge pump (c type bias) of the lcd. the lcd bias type must select the r type by option. ht46r65/ht46c65 rev. 1.80 3 july 14, 2005 3 2 4 6 . ' 3 2 4 6 . ' 3 2 4 6 . ' 3 2 4 6 . ' 3 2 4 6 . 3 ' 6 6 6 6 6 3 6 2 6 4 6 6 6 . . ' . . . . . 3 . 2 . 4 . 6 . . ' ' 6 ' 4 . 4 6 4 4 4 2 4 3 4 4 4 4 4 ' 2 . 2 6 2 4 2 2 2 3 2 2 2 2 2 ' 3 . 3 6 3 4 3 2 3 3 3 3 3 3 " 3 " 2 " 4 + ' - " ' + - " + - " + - " + - " + 3 - " 3 + 2 - " 2 + 4 - " 4 ' - ( ' - ( - ( - ( - ' 3 - 2 - ' 4 - ' 3 2 4 6 . - ' ' " ! $ . ' 3 2 4 6 . ' 3 2 4 6 . 6 4 2 3 ' " ' - + 5 " - + 5 " " - / " 3 2 3 3 3 3 3 3 3 ' . 6 4 2 3 ' . 6 4 2 3 ' . 3 2 4 6 . ' 3 2 4 6 . ' 3 2 4 6 " ' - + 5 " - + 5 " " - / " " 3 " 2 " 4 + ' - " ' + - " + - " + - " + - " + 3 - " 3 ' - ( ' - ( - ( - ' 3 - 2 - ' $ " ! ' 2 4 6 . ' 3 2 4 6 . ' - ' " 3 " 2 " 4 + ' - " ' + - " + - " + - " + - " + 3 - " 3 ' - ( ' - ( - ( . ' 3 2 4 6 . ' 3 2 4 6 . ' 3 2 4 6 . ' 3 2 4 6 . 6 . 3 ' 3 3 3 2 4 6 . ' ' 3 2 4 6 4 " ' - + 5 " - + 5 " " - / " - ' ' " ! $ 2 - ' 3 - - ' pin description pin name i/o options description pa0/bz pa1/bz pa2 pa3/pfd pa4~pa7 i/o wake-up pull-high buzzer pfd bidirectional 8-bit input/output port. each bit can be configured as wake-up in - put by rom code option. software instructions determine the cmos output or schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option). the bz, bz and pfd are pin-shared with pa0, pa1 and pa3, respectively. pb0/an0 pb1/an1 pb2/an2 pb3/an3 pb4/an4 pb5/an5 pb6/an6 pb7/an7 i/o pull-high bidirectional 8-bit input/output port. software instructions determine the cmos output, schmitt trigger input with or without pull-high resistor (deter - mined by pull-high option: bit option) or a/d input. once a pb line is selected as an a/d input (by using software control), the i/o function and pull-high re - sistor are disabled automatically. pd0/pwm0 pd1/pwm1 pd2/pwm2 pd3/pwm3 i/o pull-high pwm bidirectional 4-bit input/output port. software instructions determine the cmos output, schmitt trigger input with or without a pull-high resistor (deter - mined by pull-high option: bit option). the pwm0/pwm1/pwm2/pwm3 out - put function are pin-shared with pd0/pd1/pd2/pd3 (dependent on pwm options). pd4/int0 pd5/int1 pd6/tmr0 pd7/tmr1 i/o pull-high bidirectional 4-bit input/output port. software instructions determine the cmos output, schmitt trigger input with or without a pull-high resistor (deter - mined by pull-high option: bit option). the int0 , int1 , tmr0 and tmr1 are pin-shared with pd4/pd5/pd6/pd7. vss negative power supply, ground vlcd i lcd power supply vmax i ic maximum voltage connect to vdd, vlcd or v1 v1, v2, c1, c2 i voltage pump com0~com2 com3/seg40 o 1 / 3or1 / 4 duty seg40 can be set as a segment or as a common output driver for lcd panel by options. com0~com2 are outputs for lcd panel plate. seg0~seg39 o logical output lcd driver outputs for lcd panel segments. seg0~seg23 can be optioned as logical outputs. osc1 osc2 i o crystal or rc osc1 and osc2 are connected to an rc network or a crystal (by options) for the internal system clock. in the case of rc operation, osc2 is the output ter - minal for 1 / 4 system clock. the system clock may come from the rtc oscilla - tor. if the system clock comes from rtcosc, these two pins can be floating. osc3 osc4 i o rtc or system clock real time clock oscillators. osc3 and osc4 are connected to a 32768hz crystal oscillator for timing purposes or to a system clock source (depending on the options). no built-in capacitor vdd positive power supply res i schmitt trigger reset input, active low absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. ht46r65/ht46c65 rev. 1.80 4 july 14, 2005 d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =8mhz 3.3 5.5 v i dd1 operating current (crystal osc, rc osc) 3v no load, adc off, f sys =4mhz 12ma 5v 35ma i dd2 operating current (crystal osc, rc osc) 5v no load, adc off, f sys =8mhz 48ma i dd3 operating current (f sys =32768hz) 3v no load, adc off 0.3 0.6 ma 5v 0.6 1 ma i stb1 standby current (*f s =t1) 3v no load, system halt, lcd off at halt 1 a 5v 2 a i stb2 standby current (*f s =rtc osc) 3v no load, system halt, lcd on at halt, c type 2.5 5 a 5v 10 20 a i stb3 standby current (*f s =wdt osc) 3v no load, system halt, lcd on at halt, c type 25 a 5v 610 a i stb4 standby current (*f s =rtc osc) 3v no load, system halt, lcd on at halt, r type, 1 / 2 bias, v lcd =v dd (low bias current option) 17 30 a 5v 34 60 a i stb5 standby current (*f s =rtc osc) 3v no load, system halt, lcd on at halt, r type, 1 / 3 bias, v lcd =v dd (low bias current option) 13 25 a 5v 28 50 a i stb6 standby current (*f s =wdt osc) 3v no load, system halt, lcd on at halt, r type, 1 / 2 bias, v lcd =v dd (low bias current option) 14 25 a 5v 26 50 a i stb7 standby current (*f s =wdt osc) 3v no load, system halt, lcd on at halt, r type, 1 / 3 bias, v lcd =v dd (low bias current option) 10 20 a 5v 19 40 a v il1 input low voltage for i/o ports, tmr0, tmr1, int0 and int1 0 0.3v dd v v ih1 input high voltage for i/o ports, tmr0, tmr1, int0 and int1 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr low voltage reset voltage 2.7 3.0 3.3 v v lvd low voltage detector voltage 3.0 3.3 3.6 v i ol1 i/o port segment logic output sink current 3v v ol =0.1v dd 612 ma 5v 10 25 ma i oh1 i/o port segment logic output source current 3v v oh =0.9v dd 2 4 ma 5v 5 8 ma ht46r65/ht46c65 rev. 1.80 5 july 14, 2005 symbol parameter test conditions min. typ. max. unit v dd conditions i ol2 lcd common and segment current 3v v ol =0.1v dd 210 420 a 5v 350 700 a i oh2 lcd common and segment current 3v v oh =0.9v dd 80 160 a 5v 180 360 a r ph pull-high resistance of i/o ports and int0 , int1 3v 20 60 100 k 5v 10 30 50 k v ad a/d input voltage 0 v dd v e ad a/d conversion integral nonlinearity error 0.5 1 lsb i adc additional power consumption if a/d converter is used 3v 0.5 1 ma 5v 1.5 3 ma note: *f s please refer to clock option of watchdog timer a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz f sys2 system clock (32768hz crystal osc) 2.2v~5.5v 32768 hz f rtcosc rtc frequency 32768 hz f timer timer i/p frequency (tmr0/tmr1) 2.2v~5.5v 0 4000 khz 3.3v~5.5v 0 8000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t res external reset low pulse width 1 s t sst system start-up timer period power-up or wake-up from halt 1024 t sys t lvr low voltage width to reset 1 ms t int interrupt pulse width 1 s t ad a/d clock period 1 s t adc a/d conversion time 76 t ad t adcs a/d sampling time 32 t ad note: t sys = 1/f sys ht46r65/ht46c65 rev. 1.80 6 july 14, 2005 ht46r65/ht46c65 rev. 1.80 7 july 14, 2005 functional description execution flow the system clock is derived from either a crystal or an rc oscillator or a 32768hz crystal oscillator. it is inter - nally divided into four non-overlapping clocks. one in - struction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. the pipelining scheme makes it possible for each in - struction to be effectively executed in a cycle. if an in - struction changes the value of the program counter, two cycles are required to complete the instruction. program counter pc the program counter (pc) is 13 bits wide and it controls the sequence in which the instructions stored in the pro - gram rom are executed. the contents of the pc can specify a maximum of 8192 addresses. after accessing a program memory word to fetch an in - struction code, the value of the pc is incremented by 1. the pc then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading a pcl register, a subroutine call, an ini - tial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; oth - erwise proceed to the next instruction. / % ) ) ; < = ) ) ; 7 < / % ) ) ; > < = ) ) ; < / % ) ) ; > < = ) ) ; > < > > # ) 1 ? ) ; ) 1 # < execution flow mode program counter *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0000000000000 external interrupt 0 0000000000100 external interrupt 1 0000000001000 timer/event counter 0 overflow 0000000001100 timer/event counter 1 overflow 0000000010000 time base interrupt 0000000010100 rtc interrupt 0000000011000 skip program counter+2 loading pcl *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *12~*0: program counter bits s12~s0: stack register bits #12~#0: instruction code bits @7~@0: pcl bits ht46r65/ht46c65 rev. 1.80 8 july 14, 2005 the lower byte of the pc (pcl) is a readable and writeable register (06h). moving data into the pcl per - forms a short jump. the destination is within 256 loca - tions. when a control transfer takes place, an additional dummy cycle is required. program memory eprom the program memory (eprom) is used to store the pro - gram instructions which are to be executed. it also con - tains data, table, and interrupt entries, and is organized into 8192 16 bits which are addressed by the program counter and table pointer. certain locations in the rom are reserved for special usage: location 000h location 000h is reserved for program initialization. after chip reset, the program always begins execution at this location. location 004h location 004h is reserved for the external interrupt service program. if the int0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004h. location 008h location 008h is reserved for the external interrupt service program also. if the int1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008h. location 00ch location 00ch is reserved for the timer/event coun - ter 0 interrupt service program. if a timer interrupt re - sults from a timer/event counter 0 overflow, and if the interrupt is enabled and the stack is not full, the pro - gram begins execution at location 00ch. location 010h location 010h is reserved for the timer/event coun - ter 1 interrupt service program. if a timer interrupt re - sults from a timer/event counter 1 overflow, and if the interrupt is enabled and the stack is not full, the pro - gram begins execution at location 010h. location 014h location 014h is reserved for the time base interrupt service program. if a time base interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014h. location 018h location 018h is reserved for the real time clock inter - rupt service program. if a real time clock interrupt oc - curs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 018h. table location any location in the rom can be used as a look-up ta- ble. the instructions tabrdc [m] (the current page, 1 page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to tblh (table higher-order byte register) (08h). only the destination of the lower-order byte in the table is well-defined; the other bits of the ta - ble word are all transferred to the lower portion of tblh. the tblh is read only, and the table pointer (tblp) is a read/write register (07h), indicating the ta - ble location. before accessing the table, the location should be placed in tblp. all the table related instruc - tions require 2 cycles to complete the operation. these areas may function as a normal rom depend - ing upon the user s requirements. 8 ) 1 : ) = 1 ) ) ' ) @ - 8 ) ) ' ) ) @ 2 ) @ # $ ? 7 ) @ 1 ) ; 3 2 ) a < b ) ) ) & ) ' ) ) / = 1 ) ) ) @ ) + ) ) $ ? 7 ) @ 1 ) ; 3 2 ) a < - 8 ) ) ) ) @ ' ' ' 9 ' ' 9 ' ' 6 9 ' 9 / / / 9 ' 6 9 ' ' 9 ' ' 9 / / 9 ' ' 9 program memory instruction(s) table location *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p12 p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *12~*0: table location bits p12~p8: current program counter bits @7~@0: table pointer bits ht46r65/ht46c65 rev. 1.80 9 july 14, 2005 stack register stack the stack register is a special part of the memory used to save the contents of the program counter. the stack is organized into 16 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. its activated level is indexed by a stack pointer (sp) and is neither readable nor writeable. at the start of a subroutine call or an interrupt acknowledg - ment, the contents of the program counter is pushed onto the stack. at the end of the subroutine or interrupt routine, signaled by a return instruction (ret or reti), the contents of the program counter is restored to its previous value from the stack. after chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the ac - knowledgment is still inhibited. once the sp is decre - mented (by ret or reti), the interrupt is serviced. this feature prevents stack overflow, allowing the program - mer to use the structure easily. likewise, if the stack is full, and a call is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent sixteen return addresses are stored). data memory ram the data memory (ram) is designed with 417 8 bits, and is divided into two functional groups, namely; spe- cial function registers 33 8 bit and general purpose data memory, bank0: 192 8 bit and bank2: 192 8 bit most of which are readable/writeable, although some are read only. the special function register are overlapped in any banks. of the two types of functional groups, the special func- tion registers consist of an indirect addressing register 0 (00h), a memory pointer register 0 (mp0;01h), an indi - rect addressing register 1 (02h), a memory pointer reg - ister 1 (mp1;03h), a bank pointer (bp;04h), an accumulator (acc;05h), a program counter lower-order byte register (pcl;06h), a table pointer (tblp;07h), a table higher-order byte register (tblh;08h), a real time clock control register (rtcc;09h), a status register (status;0ah), an inter - rupt control register 0 (intc0;0bh), a timer/event counter 0 (tmr0h:0ch; tmr0l:0dh), a timer/event counter 0 control register (tmr0c;0eh), a timer/event counter 1 (tmr1h:0fh;tmr1l:10h), a timer/event counter 1 control register (tmr1c; 11h), interrupt con - trol register 1 (intc1;1eh) , pwm data register (pwm0;1ah, pwm1;1bh, pwm2;1ch, pwm3;1dh), the a/d result lower-order byte register (adrl;24h), the a/d result higher-order byte register (adrh;25h), the a/d control register (adcr;26h), the a/d clock setting register (acsr;27h), i/o registers (pa;12h, pb;14h, pd;18h) and i/o control registers (pac;13h, pbc;15h, pdc;19h). the remaining space before the 40h is re - served for future expanded usage and reading these lo - cations will get 00h . the space before 40h is overlapping in each bank. the general purpose data memory, addressed from 40h to ffh (bank0; bp=0 or bank2; bp=2), is used for data and control information under instruction commands. all of the data memory ar - eas can handle arithmetic, logic, increment, decrement and rotate operations directly. except for some dedi - cated bits, each bit in the data memory can be set and 1 ) ) # ' ' 9 ' 9 ' 9 ' 9 ' 9 ' 3 9 ' 2 9 ' 4 9 ' 6 9 ' . 9 ' " 9 ' + 9 ' 9 ' 9 ' 9 ' / 9 ' 9 9 9 9 9 3 9 2 9 4 9 6 9 . 9 " 9 + 9 9 9 9 / 9 b ) ) ) c ' ' c 1 ) ) # ; 6 ) + # < / / 9 ' 9 ) " ) ) ' ' ) " ) ) + " $ + $ + $ 9 " ' ' 9 ' $ ' 9 $ " " + + ( ' ( ( ( " $ " 9 " " ' 9 9 9 9 9 3 9 2 9 4 9 6 9 / 9 ram mapping ht46r65/ht46c65 rev. 1.80 10 july 14, 2005 reset by set [m].i and clr [m].i . they are also indi - rectly accessible through memory pointer registers (mp0;01h/mp1;03h). the space before 40h is overlap - ping in each bank. after first setting up bp to the value of 01h or 02h to access either bank 1 or bank 2 respectively, these banks must then be accessed indirectly using the memory pointer mp1. with bp set to a value of either 01h or 02h , using mp1 to indirectly read or write to the data memory areas with addresses from 40h~ffh will result in operations to either bank 1 or bank 2. directly ad - dressing the data memory will always result in bank 0 being accessed irrespective of the value of bp. indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] and [02h] accesses the ram pointed to by mp0 (01h) and mp1(03h) respectively. reading lo - cation 00h or 02h indirectly returns the result 00h. while, writing it indirectly leads to no operation. the function of data movement between two indirect ad - dressing registers is not supported. the memory pointer registers, mp0 and mp1, are both 8-bit registers used to access the ram by combining corresponding indirect addressing registers. mp0 can only be applied to data memory, while mp1 can be applied to data memory and lcd display memory. accumulator acc the accumulator (acc) is related to the alu opera- tions. it is also mapped to location 05h of the ram and is capable of operating with immediate data. the data movement between two data memory locations must pass through the acc. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera - tions and provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz etc.) the alu not only saves the results of a data operation but also changes the status register. status register status the status register (0ah) is 8 bits wide and contains, a carry flag (c), an auxiliary carry flag (ac), a zero flag (z), an overflow flag (ov), a power down flag (pdf), and a watchdog time-out flag (to). it also records the status information and controls the operation sequence. except for the to and pdf flags, bits in the status reg - ister can be altered by instructions similar to other reg - isters. data written into the status register does not alter the to or pdf flags. operations related to the status register, however, may yield different results from those intended. the to and pdf flags can only be changed by a watchdog timer overflow, chip power-up, or clear - ing the watchdog timer and executing the halt in- struction. the z, ov, ac, and c flags reflect the status of the latest operations. on entering the interrupt sequence or executing the subroutine call, the status register will not be automati- cally pushed onto the stack. if the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a ro - tate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by either a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6, 7 unused bit, read as 0 status (0ah) register ht46r65/ht46c65 rev. 1.80 11 july 14, 2005 interrupts the device provides two external interrupts, two internal timer/event counter interrupts, an internal time base in - terrupt, and an internal real time clock interrupt. the in - terrupt control register 0 (intc0;0bh) and interrupt control register 1 (intc1;1eh) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. once an interrupt subroutine is serviced, other inter - rupts are all blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. if a certain interrupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc0 or of intc1 may be set in order to allow interrupt nesting. once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is en - abled, until the sp is decremented. if immediate service is desired, the stack should be prevented from becom - ing full. all these interrupts can support a wake-up function. as an interrupt is serviced, a control transfer occurs by pushing the contents of the program counter onto the stack followed by a branch to a subroutine at the speci - fied location in the rom. only the contents of the pro- gram counter is pushed onto the stack. if the contents of the register or of the status register (status) is altered by the interrupt service program which corrupts the de- sired control sequence, the contents should be saved in advance. external interrupts are triggered by a an edge transition of int0 or int1 (rom code option: high to low, low to high, low to high or high to low), and the related interrupt request flag (eif0; bit 4 of intc0, eif1; bit 5 of intc0) is set as well. after the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04h or 08h occurs. the interrupt request flag (eif0 or eif1) and emi bits are all cleared to disable other maskable interrupts. the internal timer/event counter 0 interrupt is initial - ized by setting the timer/event counter 0 interrupt re - quest flag (t0f; bit 6 of intc0), which is normally caused by a timer overflow. after the interrupt is en - abled, and the stack is not full, and the t0f bit is set, a subroutine call to location 0ch occurs. the related inter - rupt request flag (t0f) is reset, and the emi bit is cleared to disable other maskable interrupts. timer/event counter 1 is operated in the same manner but its related interrupt request flag is t1f (bit 4 of intc1) and its subroutine call location is 10h. the time base interrupt is initialized by setting the time base interrupt request flag (tbf; bit 5 of intc1), that is caused by a regular time base signal. after the interrupt is enabled, and the stack is not full, and the tbf bit is set, a subroutine call to location 14h occurs. the related interrupt request flag (tbf) is reset and the emi bit is cleared to disable further maskable interrupts. bit no. label function 0 emi control the master (global) interrupt (1=enabled; 0=disabled) 1 eei0 control the external interrupt 0 (1=enabled; 0=disabled) 2 eei1 control the external interrupt 1 (1=enabled; 0=disabled) 3 et0i control the timer/event counter 0 interrupt (1=enabled; 0=disabled) 4 eif0 external interrupt 0 request flag (1=active; 0=inactive) 5 eif1 external interrupt 1 request flag (1=active; 0=inactive) 6 t0f internal timer/event counter 0 request flag (1=active; 0=inactive) 7 for test mode used only. must be written as 0 ; otherwise may result in unpredictable operation. intc0 (0bh) register bit no. label function 0 et1i control the timer/event counter 1 interrupt (1=enabled; 0=disabled) 1 etbi control the time base interrupt (1=enabled; 0:disabled) 2 erti control the real time clock interrupt (1=enabled; 0:disabled) 3, 7 unused bit, read as 0 4 t1f internal timer/event counter 1 request flag (1=active; 0=inactive) 5 tbf time base request flag (1=active; 0=inactive) 6 rtf real time clock request flag (1=active; 0=inactive) intc1 (1eh) register ht46r65/ht46c65 rev. 1.80 12 july 14, 2005 the real time clock interrupt is initialized by setting the real time clock interrupt request flag (rtf; bit 6 of intc1), that is caused by a regular real time clock sig - nal. after the interrupt is enabled, and the stack is not full, and the rtf bit is set, a subroutine call to location 18h occurs. the related interrupt request flag (rtf) is reset and the emi bit is cleared to disable further maskable interrupts. during the execution of an interrupt subroutine, other maskable interrupt acknowledgments are all held until the reti instruction is executed or the emi bit and the related interrupt control bit are set both to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti sets the emi bit and en - ables an interrupt service, but ret does not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses are serviced on the latter of the two t2 pulses if the corresponding interrupts are enabled. in the case of simultaneous requests, the priorities in the following table apply. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 0 1 04h external interrupt 1 2 08h timer/event counter 0 overflow 3 0ch timer/event counter 1 overflow 4 10h time base interrupt 5 14h real time clock interrupt 6 18h the timer/event counter 0 interrupt request flag (t0f), external interrupt 1 request flag (eif1), external inter- rupt 0 request flag (eif0), enable timer/event counter 0 interrupt bit (et0i), enable external interrupt 1 bit (eei1), enable external interrupt 0 bit (eei0), and en - able master interrupt bit (emi) make up of the interrupt control register 0 (intc0) which is located at 0bh in the ram. the real time clock interrupt request flag (rtf), time base interrupt request flag (tbf), timer/event counter 1 interrupt request flag (t1f), enable real time clock interrupt bit (erti), and enable time base interrupt bit (etbi), enable timer/event counter 1 interrupt bit (et1i) on the other hand, constitute the interrupt control register 1 (intc1) which is located at 1eh in the ram. emi, eei0, eei1, et0i, et1i, etbi, and erti are all used to control the enable/disable status of interrupts. these bits prevent the requested i nterrupt from being serviced. once the interrupt request flags (rtf, tbf, t0f, t1f, eif1, eif0) are all set, they remain in the intc1 or intc0 respectively until the interrupts are serviced or cleared by a software instruction. it is recommended that a program should not use the call subroutine within the interrupt subroutine. it sbe - cause interrupts often occur in an unpredictable manner or require to be serviced immediately in some applica - tions. during that period, if only one stack is left, and en - abling the interrupt is not well controlled, operation of the call in the interrupt subroutine may damage the origi - nal control sequence. oscillator configuration the device provides three oscillator circuits for system clocks, i.e., rc oscillator, crystal oscillator and 32768hz crystal oscillator, determined by options. no matter what type of oscillator is selected, the signal is used for the system clock. the halt mode stops the system oscilla - tor (rc and crystal oscillator only) and ignores external signal in order to conserve power. the 32768hz crystal oscillator still runs at halt mode. if the 32768hz crystal oscillator is selected as the system oscillator, the system oscillator is not stopped; but the instruction execution is stopped. since the 32768hz oscillator is also designed for timing purposes, the internal timing (rtc, time base, wdt) operation still runs even if the system enters the halt mode. of the three oscillators, if the rc oscillator is used, an external resistor between osc1 and vss is required, and the range of the resistance should be from 30k to 750k . the system clock, divided by 4, is available on osc2 with pull-high resistor, which can be used to syn - chronize external logic. the rc oscillator provides the most cost effective solution. however, the frequency of the oscillation may vary with vdd, temperature, and the chip itself due to process variations. it is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. # 1 ) 1 1 4 2 6 9 : ) # 1 - ) 1 1 ) 1 1 & 0 - 4 ' / system oscillator note: 32768hz crystal enable condition: for wdt clock source or for system clock source. the external resistor and capacitor components connected to the 32768hz crystal are not necessary to pro - vide oscillation. for applications where precise rtc frequencies are essential, these components may be re - quired to provide frequency compensation due to different crystal manufacturing tolerances. ht46r65/ht46c65 rev. 1.80 13 july 14, 2005 on the other hand, if the crystal oscillator is selected, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. a resonator may be connected between osc1 and osc2 to replace the crystal and to get a frequency reference, but two ex - ternal capacitors in osc1 and osc2 are required. there is another oscillator circuit designed for the real time clock. in this case, only the 32.768khz crystal oscil - lator can be applied. the crystal should be connected between osc3 and osc4. the rtc oscillator circuit can be controlled to oscillate quickly by setting the qosc bit (bit 4 of rtcc). it is recommended to turn on the quick oscillating function upon power on, and then turn it off after 2 seconds. the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. although the system enters the power down mode, the system clock stops, and the wdt oscillator still works with a pe - riod of approximately 65 s at 5v. the wdt oscillator can be disabled by options to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (rtc os- cillator). the timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the wdt can be disabled by options. but if the wdt is disabled, all exe- cutions related to the wdt lead to no operation. once an internal wdt oscillator (rc oscillator with pe- riod 65 s at 5v normally) is selected, it is divided by 2 12 ~2 15 (by rom code option to get the wdt time-out period). the minimum period of wdt time-out period is about 300ms~600ms. this time-out period may vary with temperature, vdd and process variations. by se - lection the wdt rom code option, longer time-out peri - ods can be realized. if the wdt time-out is selected 2 15 , the maximum time-out period is divided by 2 15 ~2 16 about 2.1s~4.3s. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and oper - ate in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the logic can only be restarted by exter - nal logic. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recommended, since the halt will stop the system clock. the wdt overflow under normal operation initializes a chip reset and sets the status bit to . in the halt mode, the overflow initializes a warm reset , and only the program counter and sp are reset to zero. to clear the contents of the wdt, there are three methods to be adopted, i.e., external reset (a low level to res ), soft - ware instruction, and a halt instruction. there are two types of software instructions; clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruction, only one type of instruction can be active at a time depending on the options clr wdt times selection option. if the clr wdt is se - lected (i.e., clr wdt times equal one), any execution of the clr wdt instruction clears the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e., clr wdt times equal two), these two instructions have to be executed to clear the wdt; otherwise, the wdt may reset the chip due to time-out. multi-function timer the ht46r65/ht46c65 provides a multi-function timer for the wdt, time base and rtc but with different time-out periods. the multi-function timer consists of an 8-stage divider and a 7-bit prescaler, with the clock source coming from the wdt osc or rtc osc or the instruction clock (i.e., system clock divided by 4). the multi-function timer also provides a selectable fre- quency signal (ranges from f s /2 2 to f s /2 8 ) for lcd driver circuits, and a selectable frequency signal (ranging from f s /2 2 to f s /2 9 ) for the buzzer output by options. it is rec- ommended to select a nearly 4khz signal for the lcd driver circuits to have proper display. time base the time base offers a periodic time-out period to gener - ate a regular internal interrupt. its time-out period ranges from 2 12 /f s to 2 15 /f s selected by options. if time base time-out occurs, the related interrupt request flag (tbf; bit 5 of intc1) is set. but if the interrupt is en - abled, and the stack is not full, a subroutine call to loca - tion 14h occurs. 7 ) 3 - & , 2 - & - & , 3 - & - & , - & - & , - & # ) 1 ? - 8 ( ) 1 ( ? 9 : 4 2 6 9 : * * & ( 1 ? ) & - 6 watchdog timer ht46r65/ht46c65 rev. 1.80 14 july 14, 2005 real time clock rtc the real time clock (rtc) is operated in the same man - ner as the time base that is used to supply a regular in - ternal interrupt. its time-out period ranges from f s /2 8 to f s /2 15 by software programming . writing data to rt2, rt1 and rt0 (bit 2, 1, 0 of rtcc;09h) yields various time-out periods. if the rtc time-out occurs, the related interrupt request flag (rtf; bit 6 of intc1) is set. but if the interrupt is enabled, and the stack is not full, a sub - routine call to location 18h occurs. rt2 rt1 rt0 rtc clock divided factor 000 2 8 * 001 2 9 * 010 2 10 * 011 2 11 * 100 2 12 101 2 13 110 2 14 111 2 15 note: * not recommended to be used power down operation halt the halt mode is initialized by the halt instruction and results in the following. the system oscillator turns off but the wdt oscillator keeps running (if the wdt oscillator or the real time clock is selected). the contents of the on-chip ram and of the registers remain unchanged. the wdt is cleared and start recounting (if the wdt clock source is from the wdt oscillator or the real time clock oscillator). all i/o ports maintain their original status. the pdf flag is set but the to flag is cleared. lcd driver is still running (if the wdt osc or rtc osc is selected). the system quits the halt mode by an external reset, an interrupt, an external falling edge signal on port a, or a wdt overflow. an external reset causes device initial - ization, and the wdt overflow performs a warm reset . after examining the to and pdf flags, the reason for chip reset can be determined. the pdf flag is cleared by system power-up or by executing the clr wdt in - struction, and is set by executing the halt instruction. on the other hand, the to flag is set if wdt time-out oc - curs, and causes a wake-up that only resets the pro - gram counter and sp, and leaves the others at their original state. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by options. awakening from an i/o port stimulus, the program resumes execution of the next instruction. on the other hand, awakening from an interrupt, two se- quence may occur. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program resumes execution at the next instruction. but if the in- terrupt is enabled, and the stack is not full, the regular in- terrupt response takes place. when an interrupt request flag is set before entering the halt status, the system cannot be awakened using that interrupt. if wake-up events occur, it takes 1024 t sys (system clock period) to resume normal operation. in other words, a dummy period is inserted after the wake-up. if the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. however, if the wake-up results in the next instruction execution, the execution will be per - formed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. 8 ) ) ) ) ) ) ) ) & 6 ) ) = d 1 ' ) 6 - & , 3 - & real time clock ) ) ) ) ) ) ) ) & 8 1 ) ) $ ) 8 ) ; & - , & - 6 < + : : ) ; & - , & - . < ) + ) - & , 3 - & time base ht46r65/ht46c65 rev. 1.80 15 july 14, 2005 reset there are three ways in which reset may occur. res is reset during normal operation res is reset during halt wdt time-out is reset during normal operation the wdt time-out during halt differs from other chip reset conditions, for it can perform a warm reset that resets only the program counter and sp and leaves the other circuits at their original state. some registers re - main unaffected during any other reset conditions. most registers are reset to the initial condition once the re - set conditions are met. examining the pdf and to flags, the program can distinguish between different chip resets . to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys- tem awakes from the halt state or during power up. awaking from the halt state or system power-up, the sst delay is added. an extra sst delay is added during the power-up pe- riod, and any wake-up from halt may enable only the sst delay. the functional unit chip reset status is shown below. program counter 000h interrupt disabled prescaler, divider cleared wdt, rtc, time base cleared. after master reset, wdt starts counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack ' ' ? ' ? ' d / e ' d ' / e reset circuit note: * make the length of the wiring, which is con - nected to the res pin as short as possible, to avoid noise interference. ) 7 % ) ) > reset timing chart ( 9 " $ ( 7 = 1 1 a 7 ) ' 7 @ ) 1 ( ) reset configuration ht46r65/ht46c65 rev. 1.80 16 july 14, 2005 the register states are summarized below: register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu bp 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 0000h 0000h 0000h 0000h 0000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu rtcc --00 0111 --00 0111 --00 0111 --00 0111 --uu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmr0h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu tmr1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pwm0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pwm3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu intc1 -000 -000 -000 -000 -000 -000 -000 -000 -uuu -uuu adrl xx-- ---- xx-- ---- xx-- ---- xx-- ---- uu-- ---- adrh xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu acsr 1--- --00 1--- --00 1--- --00 ---- --00 u--- --uu note: * stands for warm reset u stands for unchanged x stands for unknown ht46r65/ht46c65 rev. 1.80 17 july 14, 2005 timer/event counter two timer/event counters (tmr0,tmr1) are imple - mented in the microcontroller. the timer/event counter 0 contains a 16-bit programmable count-up counter and the clock may come from an external source or an inter - nal clock source. an internal clock source comes from f sys . the timer/event counter 1 contains a 16-bit pro - grammable count-up counter and the clock may come from an external source or an internal clock source. an internal clock source comes from f sys /4 or 32768hz se - lected by option. the external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. there are six registers related to the timer/event coun - ter 0; tmr0h (0ch), tmr0l (0dh), tmr0c (0eh) and the timer/event counter 1; tmr1h (0fh), tmr1l (10h), tmr1c (11h). writing tmr0l (tmr1l) will only put the written data to an internal lower-order byte buffer (8-bit) and writing tmr0h (tmr1h) will transfer the specified data and the contents of the lower-order byte buffer to tmr0h (tmr1h) and tmr0l (tmr1l) regis - ters, respectively. the timer/event counter 1/0 preload register is changed by each writing tmr0h (tmr1h) operations. reading tmr0h (tmr1h) will latch the contents of tmr0h (tmr1h) and tmr0l (tmr1l) counters to the destination and the lower-order byte buffer, respectively. reading the tmr0l (tmr1l) will read the contents of the lower-order byte buffer. the tmr0c (tmr1c) is the timer/event counter 0 (1) con - trol register, which defines the operating mode, counting enable or disable and an active edge. the t0m0, t0m1 (tmr0c) and t1m0, t1m1 (tmr1c) bits define the operation mode. the event count mode is used to count external events, which means that the clock source is from an external (tmr0, tmr1) pin. the timer mode functions as a normal timer with the clock source coming from the internal selected clock source. finally, the pulse width measurement mode can be used to count the high or low level duration of the external sig - nal (tmr0, tmr1), and the counting is based on the in - ternal selected clock source. in the event count or timer mode, the timer/event coun - ter starts counting at the current contents in the timer/event counter and ends at ffffh. once an over - ' ' ' ' ' ' ' ' ' 1 ) ( % ) 1 6 7 ) 1 6 7 ) ! & 0 & ' , ' ' ; 2 > < ) ) ; 4 > < ( ) ' - - - ) 2 7 + 1 ) ) + 1 8 & 1 a ) ) $ a ) + # + & & 9 % ) + # $ a ) + # 2 7 + ) - 8 ) / ' timer/event counter 0 ' ' 1 ) ( % ) 1 & & 0 - 4 2 6 9 : ! 2 7 + 1 ) ) + 1 8 & 1 a ) ) $ a ) + # + & & 9 % ) + # $ a ) + # 2 7 + ) - 8 ) / timer/event counter 1 ! - / / ) ) " ) ) $ / ' / pfd source option ht46r65/ht46c65 rev. 1.80 18 july 14, 2005 flow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt re - quest flag (t0f; bit 6 of intc0, t1f; bit 4 of intc1). in the pulse width measurement mode with the values of the t0on/t1on and t0e/t1e bits equal to 1, after the tmr0 (tmr1) has received a transient from low to high (or high to low if the t0e/t1e bit is 0 ), it will start count - ing until the tmr0 (tmr1) returns to the original level and resets the t0on/t1on. the measured result re - mains in the timer/event counter even if the activated transient occurs again. in other words, only 1-cycle measurement can be made until the t0on/t1on is set. the cycle measurement will re-function as long as it re - ceives further transient pulse. in this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter register and issues an interrupt re - quest, as in the other two modes, i.e., event and timer modes. bit no. label function 0 1 2 t0psc0 t0psc1 t0psc2 to define the prescaler stages. t0psc2, t0psc1, t0psc0= 000: f int =f sys 001: f int =f sys /2 010: f int =f sys /4 011: f int =f sys /8 100: f int =f sys /16 101: f int =f sys /32 110: f int =f sys /64 111: f int =f sys /128 3 t0e defines the tmr0 active edge of the timer/event counter: in event counter mode (t0m1,t0m0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (t0m1,t0m0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 t0on enable/disable timer counting (0=disabled; 1=enabled) 5 unused bit, read as 0 6 7 t0m0 t0m1 defines the operating mode t0m1, t0m0= 01= event count mode (external clock) 10= timer mode (internal clock) 11= pulse width measurement mode (external clock) 00= unused tmr0c (0eh) register bit no. label function 0~2 unused bit, read as 0 3 t1e defines the tmr1 active edge of the timer/event counter: in event counter mode (t1m1,t1m0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (t1m1,t1m0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 t1on enable/disable timer counting (0= disabled; 1= enabled) 5 t1s defines the tmr1 internal clock source (0=f sys /4; 1=32768hz) 6 7 t1m0 t1m1 defines the operating mode t1m1, t1m0= 01= event count mode (external clock) 10= timer mode (internal clock) 11= pulse width measurement mode (external clock) 00= unused tmr1c (11h) register ht46r65/ht46c65 rev. 1.80 19 july 14, 2005 to enable the counting operation, the timer on bit (t0on: bit 4 of tmr0c; t1on: 4 bit of tmr1c) should be set to 1. in the pulse width measurement mode, the t0on/t1on is automatically cleared after the measure - ment cycle is completed. but in the other two modes, the t0on/t1on can only be reset by instructions. the overflow of the timer/event counter 0/1 is one of the wake-up sources and can also be applied to a pfd (pro - grammable frequency divider) output at pa3 by op - tions. only one pfd (pfd0 or pfd1) can be applied to pa3 by options. if pa3 is set as pfd output, there are two types of selections; one is pfd0 as the pfd output, the other is pfd1 as the pfd output. pfd0, pfd1 are the timer overflow signals of the timer/event counter 0, timer/event counter 1 respectively. no matter what the operation mode is, writin ga0to et0i or et1i disables the related interrupt service. when the pfd function is selected, executing set [pa].3 instruction to enable pfd output and executing clr [pa].3 instruction to disable pfd output. in the case of timer/event counter off condition, writing data to the timer/event counter preload register also re - loads that data to the timer/event counter. but if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event coun - ter preload register. the timer/event counter still contin- ues its operation until an overflow occurs. when the timer/event counter (reading tmr0/tmr1) is read, the clock is blocked to avoid errors, as this may re- sults in a counting error. blocking of the clock should be taken into account by the programmer. it is strongly rec- ommended to load a desired value into the tmr0/tmr1 register first, before turning on the related timer/event counter, for proper operation since the initial value of tmr0/tmr1 is unknown. due to the timer/event coun - ter scheme, the programmer should pay special atten - tion on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event counter function, to avoid unpredictable re - sult. after this procedure, the timer/event function can be operated normally. the bit0~bit2 of the tmr0c can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. the definitions are as shown. the overflow signal of timer/event counter can be used to generate the pfd signal. the timer prescaler is also used as the pwm counter. input/output ports there are 24 bidirectional input/output lines in the microcontroller, labeled as pa, pb and pd, which are mapped to the data memory of [12h], [14h] and [18h] respectively. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h or 18h). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pdc) to control the input/output configuration. with this control register, cmos output or schmitt trigger input with or without pull-high resistor structures can be re - configured dynamically under software control. to func - tion as an input, the corresponding latch of the control register must write 1 . the input source also depends on the control register. if the control register bit is 1 , the input will read the pad state. if the control register bit is 0 , the contents of the latches will move to the inter - nal bus. the latter is possible in the read-modify-write instruction. for output function, cmos is the only configuration. these control registers are mapped to locations 13h, 15h and 19h. after a chip reset, these input/output lines remain at high levels or floating state (depending on pull-high options). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h or 18h) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. each i/o port has a pull-high option. once the pull-high option is selected, the i/o port has a pull-high resistor, otherwise, there s none. take note that a non-pull-high i/o port operating in input mode will cause a floating state. the pa3 is pin-shared with the pfd signal. if the pfd option is selected, the output signal in output mode of pa3 will be the pfd signal generated by timer/event counter overflow signal. the input mode always retain its original functions. once the pfd option is selected, the pfd output signal is controlled by pa3 data register only. writing 1 to pa3 data register will enable the pfd output function and writing 0 will force the pa3 to remain at 0 . the i/o functions of pa3 are shown below. i/o mode i/p (normal) o/p (normal) i/p (pfd) o/p (pfd) pa3 logical input logical output logical input pfd (timer on) note: the pfd frequency is the timer/event counter overflow frequency divided by 2. the pa0, pa1, pa3, pd4, pd5, pd6 and pd7 are pin-shared with bz, bz , pfd, int0 , int1 , tmr0 and tmr1 pins respectively. ht46r65/ht46c65 rev. 1.80 20 july 14, 2005 the pa0 and pa1 are pin-shared with bz and bz signal, respectively. if the bz/bz option is selected, the output signal in output mode of pa0/pa1 will be the buzzer sig- nal generated by multi-function timer. the input mode always remain in its original function. once the bz/bz option is selected, the buzzer output signal are con- trolled by the pa0/pa1 data register only. the i/o function of pa0/pa1 are shown below. pa0i/o i i oooooooo pa1i/o i o i i i ooooo pa0 mode x x c b b c bbbb pa1 mode x c x x x c c c b b pa0 data x x d 0 1 d 0 0101 pa1 data x d x x x d1 d d x x pa0 pad status i i d 0 b d 0 0b0b pa1 pad status i d i i i d 1 dd0 b note: i input; o output d, d0, d1 data b buzzer option, bz or bz x don t care c cmos output the pb can also be used as a/d converter inputs. the a/d function will be described later. there is a pwm function shared with pd0/pd1/pd2/pd3. if the pwm function is enabled, the pwm0/pwm1/pwm2/pwm3 signal will appear on pd0/pd1/pd2/pd3 (if pd0/pd1/ pd2/pd3 is operating in output mode). writing 1 to pd0~pd3 data register will enable the pwm output function and writing 0 will force the pd0~pd3 to re - main at 0 . the i/o functions of pd0/pd1/pd2/pd3 are as shown. i/o mode i/p (normal) o/p (normal) i/p (pwm) o/p (pwm) pd0~ pd3 logical input logical output logical input pwm0~ pwm3 it is recommended that unused or not bonded out i/o lines should be set as output pins by software instruction to avoid consuming power under input floating state. the definitions of pfd control signal and pfd output frequency are listed in the following table. timer timer preload value pa3 data register pa3 pad state pfd frequency off x 0 0 x off x 1 u x on n 0 0 x on n 1 pfd f tmr /[2 (m-n)] note: x stands for unused u stands for unknown m is 65536 for pfd0 or pfd1 n is preload value for timer/event counter f tmr is input clock frequency for timer/event counter ! ! / ; " < ( ? 7 ) ' ) & ) ) 1 # ) & ) 3 ) 1 # ' ) & ) 2 ) 1 # ) & ) 4 ) 1 # # ) ( ? 7 ; " ) 1 # < ) ) " ' - " - " - ' - - - f * f * f 1 ) + 1 1 7 % % ) + ( ) 1 ) % ) ) 1 ) ( ) ) ) + " ' - + 5 " - + 5 " " - / " , " 4 + ' - " ' , + 4 - " 4 ' - ( ' - ( - ( - ( - ' 3 - 2 - ' 4 - f + 5 - + 5 - / - ( ' - ( - ( - ( input/output ports ht46r65/ht46c65 rev. 1.80 21 july 14, 2005 pwm the microcontroller provides 4 channels (6+2)/(7+1) (dependent on options) bits pwm output shared with pd0/pd1/pd2/pd3. the pwm channels have their data registers denoted as pwm0 (1ah), pwm1 (1bh), pwm2 (1ch) and pwm3 (1dh). the frequency source of the pwm counter comes from f sys . the pwm regis - ters are four 8-bit registers. the waveforms of pwm out - puts are as shown. once the pd0/pd1/pd2/pd3 are selected as the pwm outputs and the output function of pd0/pd1/pd2/pd3 are enabled (pdc.0/pdc.1/ pdc.2/pdc.3= 0 ), writing 1 to pd0/pd1/pd2/pd3 data register will enable the pwm output function and writing 0 will force the pd0/pd1/pd2/pd3 to stay at 0 . a (6+2) bits mode pwm cycle is divided into four modu - lation cycles (modulation cycle 0~modulation cycle 3). each modulation cycle has 64 pwm input clock period. in a (6+2) bit pwm function, the contents of the pwm register is divided into two groups. group 1 of the pwm register is denoted by dc which is the value of pwm.7~pwm.2. the group 2 is denoted by ac which is the value of pwm.1~pwm.0. in a (6+2) bits mode pwm cycle, the duty cycle of each modulation cycle is shown in the table. parameter ac (0~3) duty cycle modulation cycle i (i=0~3) i ! (6+2) pwm mode ! " " " " " " " " " " " " " (7+1) pwm mode ht46r65/ht46c65 rev. 1.80 22 july 14, 2005 in a (7+1) bits mode pwm cycle, the duty cycle of each modulation cycle is shown in the table. parameter ac (0~1) duty cycle modulation cycle i (i=0~1) i ht46r65/ht46c65 rev. 1.80 24 july 14, 2005 the following programming example illustrates how to setup and implement an a/d conversion. the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete. example: using eocb polling method to detect end of conversion clr eadi ; disable adc interrupt mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d clock mov a,00100000b ; setup adcr register to configure port pb0~pb3 as a/d inputs mov adcr,a ; and select an0 to be connected to the a/d converter : : ; as the port b channel bits have changed the following start ; signal (0-1-0) must be issued within 10 instruction cycles : start_conversion: clr start set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr register eocb bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a,adrh ; read conversion result high byte value from the adrh register mov adrh_buffer,a ; save result to user defined memory mov a,adrl ; read conversion result low byte value from the adrl register mov adrl_buffer,a ; save result to user defined memory : : jmp start_conversion ; start next a/d conversion " " - ) 8 ) " " - ) 8 ) " " - ) 8 ) ' ' ' + ' ' ' + ' ' + ' ' + " + , ' " , " ' a 7 ) & ) " - 8 b ) & ) + ) & b ) 1 ) 1 ) % 1 " - ) 1 ? ) ) @ ) & 0 - j ) & 0 - 6 ) ) & 0 - " i " " i 4 2 " b ) ) & ) " - 8 ) " - 8 " - ) 1 ) ) ) " ) ' ' + ' ' ' + ) & ) " - 8 ) " - 8 ' ' ' + d ) + ) ) ) ) - d ) " - ) 8 ) ) a ) & & ) ) ) ) ) ) a ) ' + ' ' + ) & ) " - 8 ) " - 8 k ) ) & ) " - 8 ) & ) " - 8 ) ) ) # 1 ) j ) = ) ) ) # 1 ) 1 1 a " - ) 1 ) ) ) " ) " - ) 1 ) ) ) " ) a/d conversion timing ht46r65/ht46c65 rev. 1.80 25 july 14, 2005 lcd display memory the device provides an area of embedded data memory for lcd display. this area is located from 40h to 68h of the ram at bank 1. bank pointer (bp; located at 04h of the ram) is the switch between the ram and the lcd display memory. when the bp is set as 1 , any data written into 40h~68h will effect the lcd display. when the bp is cleared to 0 or 2 , any data written into 40h~68h means to access the general purpose data memory. the lcd display memory can be read and written to only by indirect addressing mode using mp1. when data is written into the display data area, it is auto - matically read by the lcd driver which then generates the corresponding lcd driving signals. to turn the dis - play on or off, a 1 or a 0 is written to the correspond - ing bit of the display memory, respectively. the figure illustrates the mapping between the display memory and lcd pattern for the device. lcd driver output the output number of the device lcd driver can be 41 2or41 3or40 4 by option (i.e., 1 / 2 duty, 1 / 3 duty or 1 / 4 duty). the bias type lcd driver can be r type or c type. if the r bias type is selected, no external ca - pacitor is required. if the c bias type is selected, a ca - pacitor mounted between c1 and c2 pins is needed. the lcd driver bias voltage can be 1 / 2 bias or 1 / 3 bias by option. if 1 / 2 bias is selected, a capacitor mounted between v2 pin and ground is required. if 1 / 3 bias is se - lected, two capacitors are needed for v1 and v2 pins. refer to application diagram. ' 9 ' 9 9 9 2 2 9 2 4 9 2 6 9 + ' ' 6 . ' display memory ' ) ) ) ) $ ) ) ) ) 1 % " ) + " ) + " ) + " ) + " ) + b ) - ) # j ) - ) @ j ) ) # b ) c " c ) - ) $ j ) c + c ) $ j ) c c ) - ) $ - ) # j ) - ) @ j ) ) # b ) c " c ) $ j ) c + c ) - ) $ j ) c c ) - ) $ lcd driver output ht46r65/ht46c65 rev. 1.80 26 july 14, 2005 ' j ) j ) ! " # $ " $ ' j j ) $ ) - ) ) $ ) ) $ ) - ) ) $ ) ) " 1 1 ) ) $ ) 8 ) ) ' ) ) % $ ) - ) ) $ ) ) $ ) - ) ) $ ) ) $ ) - ) ) $ ) ) $ ) - ) ) $ ) ) $ ) - ) ) $ ) ) $ ) - ) ) $ ) ) $ ) - ) ) $ ) ) $ ) - ) ) $ ) ) $ ) - ) ) $ ) ) $ ) - ) ) $ ) ) $ ) - ) ) $ ) ) $ ) - ) ) $ ) ) $ - ) ) $ ) ) b ) c c ) ) ) % ) ) 1 j ) & ) % ) - ) # ) $ ) ) d $ ) ) ) ' j j ) ) ) ) 1 % ) 1 # ) $ ) ) ) ) ' ) ) ) 1 % ) 1 # ) $ ) ) ) ) ) ) ) 1 % 1 # ) $ ) ) ) ) ) ) ) 1 % $ ) ) ' j ) ) ) 1 % ) $ ) ) ) ) ' j ) ) ) ) 1 % ) $ ) ) j ) ) ) ) 1 % ) $ ) ) ) ' j j ) ) ) ) 1 % ) " 1 1 ) 1 ) 8 ) lcd driver output (1 / 3 duty, 1 / 2 bias, r/c type) note: the 52-pin qfp package does not support the charge pump (c type bias) of the lcd. the lcd bias type must select the r type by option. lcd segments as logical output the seg0~seg23 also can be optioned as logical output, once an lcd segment is optioned as a logical output, the content of bit0 of the related segment address in lcd ram will appear on the segment. seg0~seg7 and seg8~seg15 are together byte optioned as logical output, seg16~seg23 are bit individually optioned as logical outputs. lcd type r type c type lcd bias type 1 / 2 bias 1 / 3 bias 1 / 2 bias 1 / 3 bias v max if v dd >v lcd , then v max connect to v dd, else v max connect to v lcd if v dd > 3 2 v lcd , then v max connect to v dd , else v max connect to v1 ht46r65/ht46c65 rev. 1.80 27 july 14, 2005 low voltage reset/detector functions there is a low voltage detector (lvd) and a low voltage reset circuit (lvr) implemented in the microcontroller. these two functions can be enabled/disabled by options. once the lvd options is enabled, the user can use the rtcc.3 to enable/disable (1/0) the lvd circuit and read the lvd detector status (0/1) from rtcc.5; otherwise, the lvd function is disabled. the rtcc register definitions are listed below. bit no. label function 0~2 rt0~rt2 8 to 1 multiplexer control inputs to select the real clock prescaler output 3 lvdc lvd enable/disable (1/0) 4 qosc 32768hz osc quick start-up oscillating 0/1: quickly/slowly start 5 lvdo lvd detection output (1/0) 1: low voltage detected, read only 6, 7 unused bit, read as 0 rtcc (09h) register the lvr has the same effect or function with the exter - nal res signal which performs chip reset. during halt state, both lvr and lvd are disabled. the microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr , such as changing a battery, the lvr will au- tomatically reset the device internally. the lvr includes the following specifications: the low voltage (0.9v~v lvr ) has to remain in their original state to exceed 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and do not perform a reset function. the lvr uses the or function with the external res signal to perform chip reset. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip operation at 4mhz system clock. 3 d 3 d ' d ' d . $ 3 d 3 3 d 3 $ ' d . ' ) 1 e e 1 ) $ ) ) 1 low voltage reset note: *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. ht46r65/ht46c65 rev. 1.80 28 july 14, 2005 options the following shows the options in the device. all these options should be defined in order to ensure proper functioning system. options osc type selection. this option is to decide if an rc or crystal or 32768hz crystal oscillator is chosen as system clock. wdt, rtc and time base clock source selection. there are three types of selections: system clock/4 or rtc osc or wdt osc. wdt enable/disable selection. wdt can be enabled or disabled by option. wdt time-out period selection. there are four types of selection: wdt clock source divided by 2 12 /f s ~2 13 /f s , 2 13 /f s ~2 14 /f s ,2 14 /f s ~2 15 /f s or 2 15 /f s ~2 16 /f s . clr wdt times selection. this option defines the method to clear the wdt by instruction. one time means that the clr wdt can clear the wdt. two times means only if both of the clr wdt1 and clr wdt2 have been executed, the wdt can be cleared. time base time-out period selection. the time base time-out period ranges from 2 12 /f s to 2 15 /f s . f s means the clock source selected by options. buzzer output frequency selection. there are eight types of frequency signals for buzzer output: f s /2 2 ~f s /2 9 . f s means the clock source selected by options. wake-up selection. this option defines the wake-up capability. external i/o pins (pa only) all have the capability to wake-up the chip from a halt by a falling edge (bit option). pull-high selection. this option is to decide whether the pull-high resistance is visible or not in the input mode of the i/o ports. pa, pb and pd can be independently selected (bit option). i/o pins share with other function selections. pa0/bz , pa1/bz: pa0 and pa1 can be set as i/o pins or buzzer outputs. lcd common selection. there are three types of selections: 2 common (1 / 2 duty) or 3 common (1 / 3 duty) or 4 com- mon (1 / 4 duty). if the 4 common is selected, the segment output pin seg40 will be set as a common output. lcd bias power supply selection. there are two types of selections: 1 / 2 bias or 1 / 3 bias lcd bias type selection. this option is to determine what kind of bias is selected, r type or c type. lcd driver clock frequency selection. there are seven types of frequency signals for the lcd driver circuits: f s /2 2 ~f s /2 8 . f s stands for the clock source se - lection by options. lcd on/off at halt selection. lcd segments as logical output selection, (byte, byte, bit, bit, bit, bit, bit, bit, bit, bit option) [seg0~seg7], [seg8~seg15], seg16, seg17, seg18, seg19, seg20, seg21, seg22, or seg23 lvr selection. lvr has enable or disable options lvd selection. lvd has enable or disable options pfd selection. if pa3 is set as pfd output, there are two types of selections; one is pfd0 as the pfd output, the other is pfd1 as the pfd output. pfd0, pfd1 are the timer overflow signals of the timer/event counter 0, timer/event counter 1 respectively. pwm selection: (7+1) or (6+2) mode pd0: level output or pwm0 output pd1: level output or pwm1 output pd2: level output or pwm2 output pd3: level output or pwm3 output int0 or int1 triggering edge selection: disable; high to low; low to high; low to high or high to low. lcd bias current selection: low/high driving current (for r type only). application circuits the following table shows the c1, c2 and r1 values corresponding to the different crystal values. (for reference only) crystal or resonator c1, c2 r1 4mhz crystal 0pf 10k 4mhz resonator 10pf 12k 3.58mhz crystal 0pf 10k 3.58mhz resonator 25pf 10k 2mhz crystal & resonator 25pf 10k 1mhz crystal 35pf 27k 480khz resonator 300pf 9.1k 455khz resonator 300pf 10k 429khz resonator 300pf 10k the function of the resistor r1 is to ensure that the oscillator will switch off should low voltage condi - tions occur. such a low voltage, as mentioned here, is one which is less than the lowest value of the mcu operating voltage. note however that if the lvr is enabled then r1 can be removed. note: the resistance and capacitance for reset circuit should be designed in such a way as to ensure that the vdd is stable and remains within a valid operating voltage range before bringing res to high. * make the length of the wiring, which is connected to the res pin as short as possible, to avoid noise interference. vmax connect to vdd or vlcd or v1 refer to the table. lcd type r type c type lcd bias type 1 / 2 bias 1 / 3 bias 1 / 2 bias 1 / 3 bias vmax if v dd >v lcd , then vmax connect to v dd , else vmax connect to v lcd if v dd >3 / 2v lcd , then vmax connect to v dd , else vmax connect to v1 ht46r65/ht46c65 rev. 1.80 29 july 14, 2005 ' , - ' ' , . $ " $ $ ) a ) 1 # $ ' d / ' d / ' d / " ! 2 - ' 4 - - ' 3 - ' d / e ' ' ? ' d / ' d ' / e " ' - + 5 " - + 5 " " - / " , " 4 , + ' - " ' + 4 - " 4 ' - ( ' - ( , ' ? & $ & $ $ ' / ) % ) 8 1 j ) @ 1 ) @ 1 a & $ $ ' ' ? l l 4 3 ' ? & 0 - 4 ' / ' " ( ) * + & $ & $ $ ' ) ) ) 1 & # , $ 4 2 6 9 : instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none ht46r65/ht46c65 rev. 1.80 30 july 14, 2005 mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pdf to (4) ,pdf (4) to (4) ,pdf (4) none none to,pdf note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pdf are cleared. otherwise the to and pdf flags remain unchanged. ht46r65/ht46c65 rev. 1.80 31 july 14, 2005 instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) to pdf ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) to pdf ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) to pdf ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) to pdf ov z ac c addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) to pdf ov z ac c ht46r65/ht46c65 rev. 1.80 32 july 14, 2005 and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) to pdf ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) to pdf ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) to pdf ov z ac c call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack program counter+1 program counter addr affected flag(s) to pdf ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m] 00h affected flag(s) to pdf ov z ac c ht46r65/ht46c65 rev. 1.80 33 july 14, 2005 clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) to pdf ov z ac c clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pdf) and time-out bit (to) are cleared. operation wdt 00h pdf and to 0 affected flag(s) to pdf ov z ac c 00 clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which im- plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m] [m ] affected flag(s) to pdf ov z ac c ht46r65/ht46c65 rev. 1.80 34 july 14, 2005 cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) to pdf ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0 (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) to pdf ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) to pdf ov z ac c deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) to pdf ov z ac c ht46r65/ht46c65 rev. 1.80 35 july 14, 2005 halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pdf) is set and the wdt time-out bit (to) is cleared. operation program counter program counter+1 pdf 1 to 0 affected flag(s) to pdf ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m] [m]+1 affected flag(s) to pdf ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) to pdf ov z ac c jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation program counter addr affected flag(s) to pdf ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) to pdf ov z ac c ht46r65/ht46c65 rev. 1.80 36 july 14, 2005 mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) to pdf ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) to pdf ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation program counter program counter+1 affected flag(s) to pdf ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) to pdf ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) to pdf ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) to pdf ov z ac c ht46r65/ht46c65 rev. 1.80 37 july 14, 2005 ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation program counter stack affected flag(s) to pdf ov z ac c ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation program counter stack acc x affected flag(s) to pdf ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation program counter stack emi 1 affected flag(s) to pdf ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) to pdf ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) to pdf ov z ac c ht46r65/ht46c65 rev. 1.80 38 july 14, 2005 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) to pdf ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) to pdf ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) to pdf ov z ac c rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) to pdf ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) to pdf ov z ac c ht46r65/ht46c65 rev. 1.80 39 july 14, 2005 rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) to pdf ov z ac c sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) to pdf ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) to pdf ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) to pdf ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) to pdf ov z ac c ht46r65/ht46c65 rev. 1.80 40 july 14, 2005 set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) to pdf ov z ac c set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) to pdf ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) to pdf ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) to pdf ov z ac c snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) to pdf ov z ac c ht46r65/ht46c65 rev. 1.80 41 july 14, 2005 sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) to pdf ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) to pdf ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) to pdf ov z ac c swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) to pdf ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) to pdf ov z ac c ht46r65/ht46c65 rev. 1.80 42 july 14, 2005 sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) to pdf ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c ht46r65/ht46c65 rev. 1.80 43 july 14, 2005 xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) to pdf ov z ac c xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m] acc xor [m] affected flag(s) to pdf ov z ac c xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc acc xor x affected flag(s) to pdf ov z ac c ht46r65/ht46c65 rev. 1.80 44 july 14, 2005 package information 52-pin qfp (14 14) outline dimensions symbol dimensions in mm min. nom. max. a 17.3 17.5 b 13.9 14.1 c 17.3 17.5 d 13.9 14.1 e 1 f 0.4 g 2.5 3.1 h 3.4 i 0.1 j 0.73 1.03 k 0.1 0.2 0 7 ht46r65/ht46c65 rev. 1.80 45 july 14, 2005 . ' 3 4 " + 2 / 9 m * 56-pin ssop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 395 420 b 291 299 c8 12 c 720 730 d89 99 e 25 f4 10 g25 35 h4 12 0 8 ht46r65/ht46c65 rev. 1.80 46 july 14, 2005 3 2 " . 6 + / k 9 100-pin qfp (14 20) outline dimensions symbol dimensions in mm min. nom. max. a 18.50 19.20 b 13.90 14.10 c 24.50 25.20 d 19.90 20.10 e 0.65 f 0.30 g 2.50 3.10 h 3.40 i 0.10 j1 1.40 k 0.10 0.20 0 7 ht46r65/ht46c65 rev. 1.80 47 july 14, 2005 ' ' 6 6 ' 3 3 ' ' " + / 9 m * ht46r65/ht46c65 rev. 1.80 48 july 14, 2005 copyright 2005 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 43f, seg plaza, shen nan zhong road, shenzhen, china 518031 tel: 0755-8346-5589 fax: 0755-8346-5590 isdn: 0755-8346-5591 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 010-6641-0030, 6641-7751, 6641-7752 fax: 010-6641-0125 holmate semiconductor, inc. (north america sales office) 46712 fremont blvd., fremont, ca 94538 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com |
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